The present invention relates generally to a system and method of evaluating transistors, and in particular to a system and method of evaluating transistor functionality with an electron beam (e-beam).
P-type and N-type field effect transistors (FETs) are the fundamental building-blocks of CMOS circuitry. In-line evaluation of these transistors is typically performed using electrical tests, such as by applying electrical probes to small circuits such as individual transistors or functional circuits, like static random access memory (SRAM) arrays having between four to six metal layers or levels.